Integrated circuits are designed using computer-aided design (CAD) tools that generate lithography data used to form a mask set. The mask set is used in the fabrication of the integrated circuit (ic) devices.
The integrated circuit design process includes constructing the integrated circuit design out of simple circuits (standard cells) that are connected together electrically using wire interconnects. The standard cells and connections between them are stored in databases called “netlists” (i.e., lists of symbolic interconnections).
The netlist may include information describing inputs, outputs, transistors and a multitude of other electronic components, as well as the interconnectivity of the inputs, outputs, transistors and multitude of other electronic components.
As part of the computer implemented design process, the design information within a netlist is “placed and routed” by the CAD tool. The CAD tool utilizes placing and routing processes that are typically software programs executed on the CAD tool (often called placers and routers). The placer determines the optimum location of each standard cell within the integrated circuit layout on the semiconductor substrate. The placement location is optimized to reduce the distance between standard cells that are electrically connected to each other by wire interconnects such as input/output lines. This is done to minimize the area of the semiconductor substrate consumed by the integrated circuit and is also done to minimize the lengths of wire interconnects to reduce net capacitance within the design. The router optimizes the routing of input/output lines between connected standard cells so that the integrated circuit layout does not become overly congested by input/output lines.
A floorplan of an integrated circuit is a schematic representation of the tentative placement of its major functional blocks. For example, the metal bond pads of bump cells for contacting external components (often using wire bonding) are often located at the circumference of the chip of the integrated circuit. In modern electronic design processes, floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to chip design, i.e. before the placing and routing.
For advanced packaging, integrated circuits and other semiconductor devices are assembled using a lead-free bumping process that couples the bond pads of the bump cells of the semiconductor device, to external components. The advent of the lead-free bumping process, however, has created the problem of delamination of device features beneath the bond pads and within the bump cells. Delamination can occur for various components at any of various levels beneath the under bump metallization (UBM) and under the metal bond pads of the bump cells.
To address this delamination problem, various techniques have been attempted such as adding dummy vias and dummy metal beneath the UBM, and therefore beneath the bonding pad, in a bump cell. These techniques attempt to add dummy vias in the bump cells during the computer-aided design process. Such attempts to add dummy vias into bump cells during the design process conventionally involve inserting the dummy vias and dummy metal into the design after floorplanning, and after placement and routing of the active components of the device, has been executed. When dummy vias and dummy metal are added into the bump cells after floorplanning and placement and routing of the active device components, however, it is difficult to add enough via and metal structures to provide sufficient via density to avoid delamination, because of the wire congestion that already exists in the design by virtue of the placement and routing of the active integrated circuit components having already been completed.
According to one prior art example illustrated in FIG. 1, a gate-level design netlist of interconnected components of a semiconductor device is provided to a conventional CAD unit at step 3 and floorplanning of the semiconductor device is carried out, i.e., executed by the CAD unit, at step 5. At step 7, placement and routing of the semiconductor device is executed. During floorplanning and placement and routing, the computer aided design procedure attempts to provide the highest level of integration possible, integrating as many features as possible into a small area in order to minimize the semiconductor area required to build the integrated circuit or other semiconductor device, and to minimize the lengths of the wire interconnects. After floorplanning and placement and routing have taken place, instructions for the insertion of dummy via/dummy metal are provided to the CAD system at step 9. Information on conventional bump cells is provided at step 13. Placement and routing of the bump cells takes place at step 11. Since floorplanning and placement and routing of the semiconductor device have already occurred at steps 5, 7, wire congestion already exists and makes it difficult to add a sufficient number of dummy vias and dummy metal beneath the bond pads of the bump cells. The CAD process yields the lithography data used to form a mask set, at step 15, but this lithography data may be deficient in that the via density in the bump cells is insufficient to prevent delamination.
As such, according to conventional is design methods and procedures, sufficient via density cannot be attained in bump cells due to the foregoing and therefore the manufactured integrated circuit device is prone to delamination during the lead-free bumping process. The present invention addresses these shortcomings.